The present invention relates generally to integrated circuit devices, and more particularly to a circuit and method of independently adjusting the respective time delays of a plurality of digital signals to enable an internal clock signal to be utilized in capturing such digital signals at high data transfer rates.
Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (xe2x80x9cROMsxe2x80x9d) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (xe2x80x9cSRAMxe2x80x9d). The processor also communicates with input devices, output devices, and data storage devices.
Processors generally operate at a relatively high speed. Processors such as the Pentium(copyright) and Pentium II(copyright) microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a lower clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a substantially lower frequency. Currently, for example, a processor having a 300 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components.
Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 300 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.
System memory devices are generally dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (xe2x80x9cSDRAMsxe2x80x9d) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.
A solution to this operating speed disparity has been proposed in the form of a computer architecture known as a synchronous link architecture. In the synchronous link architecture, the system memory may be coupled to the processor either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, synchronous link memory devices receive command packets that include both control and address information. The synchronous link memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.
An example of a computer system 10 using the synchronous link architecture is shown in FIG. 1. The computer system 10 includes a processor 12 having a processor bus 14 coupled through a memory controller 18 and system memory bus 23 to three packetized or synchronous link dynamic random access memory (xe2x80x9cSLDRAMxe2x80x9d) devices 16a-16c. The computer system 10 also includes one or more input devices 20, such as a keypad or a mouse, coupled to the processor 12 through a bus bridge 22 and an expansion bus 24, such as an industry standard architecture (xe2x80x9cISAxe2x80x9d) bus or a peripheral component interconnect (xe2x80x9cPCIxe2x80x9d) bus. The input devices 20 allow an operator or an electronic device to input data to the computer system 10. One or more output devices 30 are coupled to the processor 12 to display or otherwise output data generated by the processor 12. The output devices 30 are coupled to the processor 12 through the expansion bus 24, bus bridge 22 and processor bus 14. Examples of output devices 24 include printers and a video display units. One or more data storage devices 38 are coupled to the processor 12 through the processor bus 14, bus bridge 22, and expansion bus 24 to store data in or retrieve data from storage media (not shown). Examples of storage devices 38 and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives.
In operation, the processor 12 sends a data transfer command via the processor bus 14 to the memory controller 18, which, in turn, communicates with the memory devices 16a-16c via the system memory bus 23 by sending the memory devices 16a-16c command packets that contain both control and address information. Data are coupled between the memory controller 18 and the memory devices 16a-16c through a data bus portion of the system memory bus 23. During a read operation, data is transferred from the packetized memory devices 16a-16c over the memory bus 23 to the memory controller 18 which, in turn, transfers the data over the processor 14 to the processor 12. The processor 12 transfers write data over the processor bus 14 to the memory controller 18 which, in turn, transfers the write data over the system memory bus 23 to the packetized memory devices 16a-16c. Although all the memory devices 16a-16c are coupled to the same conductors of the system memory bus 23, only one memory device 16a-16c at a time reads or writes data, thus avoiding bus contention on the memory bus 23. Bus contention is avoided by each of the memory devices 16a-16c on the system memory 22 having a unique identifier, and the command packet contains an identifying code that selects only one of these components.
The computer system 10 also includes a number of other components and signal lines that have been omitted from FIG. 1 in the interests of brevity. For example, the memory devices 16a-16c also receive a command clock signal to provide internal timing signals, and receive and provide respective data clock signals for clocking data into and out of the memory device, and also receive a FLAG signal signifying the start of a command packet, as will be explained in more detail below.
A typical command packet CA less than 0:39 greater than  for a packetized memory device is shown in FIG. 2 and is formed by 4 command packet words CA less than 0:9 greater than , each of which contains 10 bits of data. As will be explained in more detail below, each packet word CA less than 0:9 greater than  is applied on a command bus CA including 10 lines CA0-CA9. In FIG. 2, the four packet words CA less than 0:9 greater than  comprising a command packet CA less than 0:39 greater than  are designated PW1-PW4. The first packet word PW1 contains 7 bits of data identifying the packetized memory device 16a-16c that is the intended recipient of the command packet. As explained below, each of the packetized memory devices 16a-16c is provided with a unique ID code that is compared to the 7 ID bits in the first packet word PW1. Thus, although all of the packetized memory devices 16a-16c will receive the command packet CA less than 0:39 greater than , only the packetized memory device having an ID code that matches the 7 ID bits of the first packet word PW1 will respond to the packet.
The remaining 3 bits of the first packet word PW1 as well as 3 bits of the second packet word PW2 comprise a 6 bit command. Typical commands are read and write in a variety of modes, such as accesses to pages or banks of memory cells. The remaining 7 bits of the second packet word PW2 and portions of the third and fourth packet words PW3 and PW4 comprise a 20 bit address specifying a bank, row and column address for a memory transfer or the start of a multiple bit memory transfer. In one embodiment, the 20-bit address is divided into 3 bits of bank address, 10 bits of row address, and 7 bits of column address. Although the command packet shown in FIG. 2 is composed of 4 packet words PW1-PW4 each containing up to 10 bits, it will be understood that a command packet may contain a lesser or greater number of packet words, and each packet word may contain a lesser or greater number of bits.
The memory device 16a is shown in block diagram form in FIG. 3. Each of the memory devices 16a-16c includes a clock generator circuit 40 that receives a command clock signal CCLK and generates a large number of other clock and timing signals to control the timing of various operations in the memory device 16a. The memory device 16a also includes a command buffer 46 and an address capture circuit 48 which receive an internal clock signal ICLK, a command packet word CA less than 0:9 greater than  on a 10 bit command bus CA, and a terminal 52 receiving a FLAG signal. The clock generator 40 generates the ICLK signal in response to the CCLK signal, and the ICLK signal has a phase shift relative to the CCLK signal. A memory controller (not shown) or other device normally transmits command packet words CA less than 0:9 greater than  to the memory device 16a coincident with the command clock signal CCLK. As explained above, the command packet CA less than 0:39 greater than , which generally includes four 10-bit packet words PW1-PW4, contains control and address information for each memory transfer. The FLAG signal is transmitted coincident with each packet work CA less than 0:9 greater than  and identifies the start of a command packet CA less than 0:39 greater than . The FLAG signal also signals the start of an initialization mode of operation, as will be described in more detail below.
The command buffer 46 latches the command packet CA less than 0:39 greater than  from the command bus CA responsive to the ICLK signal, and compares at least a portion of the command packet to identifying data from an ID register 56 to determine if the packet is directed to the memory device 16a or some other memory device 16b, c. If the command buffer 46 determines that the command packet is directed to the memory device 16a, it then provides the command portion of the packet to a command decoder and sequencer 60. The command decoder and sequencer 60 generates a large number of internal control signals to control the operation of the memory device 16a during a memory transfer.
The address capture circuit 48 also receives the command packet CA less than 0:39 greater than  from the command bus CA and outputs a 20-bit address corresponding to the address portion in the command packet. The address is provided to an address sequencer 64, which generates a corresponding 3-bit bank address on bus 66, a 10-bit row address on bus 68, and a 7-bit column address on bus 70. The row and column addresses are processed by row and column address paths, as will be described in more detail below.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The packetized memory device 16a shown in FIG. 3 largely avoids this problem by using a plurality of memory banks 80, in this case eight memory banks 80a-80h. After a read from one bank 80a, the bank 80a can be precharged while the remaining banks 80b-80h are being accessed. Each of the memory banks 80a-80h receives a row address from a respective row latch/decoder/driver 82a-82h. All of the row latch/decoder/drivers 82a-82h receive the same row address from a predecoder 84 which, in turn, receives a row address from either a row address register 86 or a refresh counter 88 as determined by a multiplexer 90. However, only one of the row latch/decoder/drivers 82a-82h is active at any one time as determined by bank control logic 94 as a function of a bank address from a bank address register 96.
The column address on bus 70 is applied to a column latch/decoder 100, which supplies I/O gating signals to an I/O gating circuit 102. The I/O gating circuit 102 interfaces with columns of the memory banks 80a-80h through sense amplifiers 104. Data are coupled to or from the memory banks 80a-80h through the sense amps 104 and I/O gating circuit 102 to a data path subsystem 108 which includes a read data path 110 and a write data path 112. The read data path 110 includes a read latch 120 that stores data from the I/O gating circuit 102.
In the memory device 16a shown in FIG. 3, 72 bits of data are stored in the read latch 120. The read latch then provides four 18-bit data words to an output multiplexer 122 that sequentially supplies each of the 18-bit data words to a read FIFO buffer 124. Successive 18-bit data words are clocked into the read FIFO buffer 124 by a clock signal RCLK generated from the internal clock signal ICLK. The 18-bit data words are then clocked out of the read FIFO buffer 124 by a clock signal obtained by coupling the RCLK signal through a programmable delay circuit 126. The programmable delay circuit 126 is programmed during initialization of the memory device 16a so that the data from the memory device is received by a memory controller, processor, or other device (not shown in FIG. 3) at the proper time. The FIFO buffer 124 sequentially applies the 18-bit data words to a driver circuit 128 which, in turn, applies the 18-bit data words to a data bus DQ forming part of the processor bus 14 (see FIG. 1). The driver circuit 128 also applies one of two data clock signals DCLK0 and DCLK1 to respective data clock lines 132 and 133. The data clocks DCLK0 and DCLK1 enable a device, such as the processor 12, reading the data on the data bus DQ to be synchronized with the data. Particular bits in the command portion of the command packet CA0-CA9 determine which of the two data clocks DCLK0 and DCLK1 is applied by the driver circuit 128. It should be noted that the clock signals CCLK, DCLK0, and DCLK1 are differential clock signals that each include true and complementary signals, but for ease of explanation only one signal for each clock is illustrated and described.
The write data path 112 includes a receiver buffer 140 coupled to the data bus 130. The receiver buffer 140 sequentially applies 16-bit data words from the data bus DQ to four input registers 142, each of which is selectively enabled by a signal from a clock generator circuit 144. The clock generator circuit 144 generates these enable signals responsive to the selected one of the data clock signals DCLK0 and DCLK1. The memory controller or processor determines which data clock DCLK0 or DCLK1 will be utilized during a write operation using the command portion of a command packet CA less than 0:39 greater than  applied to the memory device 16a. As with the command clock signal CCLK and command packet, the memory controller or other device (not shown) normally transmits the data to the memory device 16a coincident with the selected one of the data clock signals DCLK0 and DCLK1. The clock generator 144 is programmed during initialization to adjust the timing of the clock signal applied to the input registers 142 relative to the selected one of the data clock signals DCLK0 and DCLK1 so that the input registers 142 can capture the write data at the proper times. In response to the clock signal generated responsive to the selected data clock DCLK0 or DCLK1, the input registers 142 sequentially store four 16-bit data words and combine them into one 64-bit data word applied to a write FIFO buffer 148. The write FIFO buffer 148 is clocked by a signal from the clock generator 144 and an internal write clock WCLK to sequentially apply 64-bit write data to a write latch and driver 150. The write latch and driver 150 applies the 64-bit write data to one of the memory banks 80a-80h through the I/O gating circuit 102 and the sense amplifiers 104.
As mentioned above, a goal of the synchronous link architecture is to allow data transfer between a processor and a memory device to occur at a significantly faster rate. It should be noted that the phrase xe2x80x9cdata transferxe2x80x9d as used herein includes all digital signals transferred to and from the memory device 16a, and thus includes signals on the CA and DQ busses as well as the FLAG signal. As the data transfer rate increases, it becomes more difficult to maintain the required timing between signals transmitted to the memory device 16a. For example, as mentioned above, the command packet CA less than 0:39 greater than  is normally transmitted to the memory device 16a coincident with the command clock signal CCLK, and the data is normally transmitted to the memory device 16a coincident with the selected one of the data clock signals DCLK0 and DCLK1. However, because of unequal signal delays and other factors, the command packet words CA less than 0:9 greater than  may not arrive at the memory device 16a coincident with the command clock signal CCLK, and write data packet words DQ less than 0:17 greater than  may not arrive at the memory device 16a coincident with the selected data clock signal DCLK0 or DCLK1. Moreover, even if these signals are actually coupled to the memory device 16a coincident with each other, this timing may be lost once they are coupled to circuits within the memory device. For example, internal signals require time to propagate to various circuitry in the memory device 16a, differences in the lengths of signal routes can cause differences in the times at which signals reach the circuitry, and differences in capacitive loading of signal lines can also cause differences in the times at which signals reach the circuitry.
The problems associated with varying arrival times can become significant at high data transfer rates and eventually limit the operating speed of the packetized memory device. For example, if the internal clock ICLK derived from the command clock CCLK does not cause each of the packet words CA less than 0:9 greater than  comprising a command packet CA less than 0:39 greater than  to be latched at the proper time, errors in the operation of the memory device 16a may result. The timing or phase shift of the internal clock signal ICLK relative to the command clock signal CCLK must have a value that enables the ICLK signal to be utilized in successfully latching each of the respective command signals CA less than 0 greater than -CA less than 9 greater than  comprising a packet word CA less than 0:9 greater than . The same is true of respective internal clock signals derived from the DCLK0 and DCLK1 signals, these internal clock signals being utilized to latch DQ less than 0 greater than -DQ less than 17 greater than  signals applied on the data bus DQ.
As the data transfer rate increases, the duration for which each signal CA less than 0 greater than -CA less than 9 greater than  in a packet word CA less than 0:9 greater than  is valid decreases by a corresponding amount, as will be understood by one skilled in the art. More specifically, the data window or xe2x80x9ceyexe2x80x9d for each of the CA less than 0 greater than -CA less than 9 greater than  signals decreases at higher data transfer rates, and the same is true for the respective data signals DQ less than 0 greater than -DQ less than 17 greater than  applied on the data bus DQ. The following discussion applies to both the CA less than 0 greater than -CA less than 9 greater than  and the DQ less than 0 greater than -DQ less than 17 greater than  signals, but only the CA less than 0 greater than -CA less than 9 greater than  signals will be discussed in more detail. As understood by one skilled in the art, the data eye for each of the CA less than 0 greater than -CA less than 9 greater than  signals defines the actual duration that each signal is valid after timing skew of the signal is considered. The timing skew of the CA less than 0 greater than -CA less than 9 greater than  signals arises from a variety of timing errors, such as loading on the lines of the CA bus and the physical lengths of such lines. FIG. 4 is a timing diagram illustrating the data eyes for a number of the CA less than 0 greater than -CA less than 9 greater than  signals, each of these signals being in the same packet word CA less than 0:9 greater than  applied on the command bus CA by the memory controller 18. The solid lines indicate the ideal CA less than 0 greater than , CA less than 1 greater than , and CA less than 9 greater than  signals, and the dashed lines indicate the potential timing skew for the actual CA less than 0 greater than , CA less than 1 greater than , and CA less than 9 greater than  signals. The data eyes DE of the CA less than 0 greater than , CA less than 1 greater than , and CA less than 9 greater than  signals are defined by time intervals t0-t3, t1-t4, and t5-t7, respectively. The timing skew reduces the data eyes DE of the CA less than 0 greater than , CA less than 1 greater than , and CA less than 9 greater than  signals and thereby reduces the valid duration during which each of these signals may be successfully captured.
As data eyes of the applied signals CA less than 0 greater than -CA less than 9 greater than  decrease at high data transfer rates, it is possible that one or more of these signals in each packet word CA less than 0:9 greater than  will have arrival times such that not all signals in a packet word are simultaneously valid at the memory device 16a, and thus cannot be successfully captured by the internal clock signal ICLK. For example, in FIG. 4, the data eye DE of the CA less than 0 greater than  signal from times t0-t3 does not overlap the data eye of the CA less than 9 greater than  signal from times t5-t7. In this situation, the signals CA less than 0 greater than  and CA less than 9 greater than  are not both valid at the memory device 16a at the same time so the packet word CA less than 0:9 greater than  cannot be successfully captured responsive to the ICLK signal. The transition of the ICLK signal at time t2 could successfully capture the CA less than 0 greater than  and CA less than 1 greater than  signals but not the CA less than 9 greater than  signal, and, conversely, the transition of the ICLK signal at time t6 could successfully capture the CA less than 9 greater than  signal but not the CA less than 0 greater than  and CA less than 1 greater than  signals, which have already gone invalid.
There is a need for successfully capturing signals applied to a packetized memory device at very high data transfer rates. Moreover, although the foregoing discussion is directed to packetized memory devices like SLDRAMs, similar problems exist in other types of integrated circuits, including other types of memory devices, as well as in any system capturing digital signals applied on a bus at very high data transfer rates.
According to one aspect of the present invention, a bus capture circuit captures digital signals applied on respective lines of a bus. Each latch has input and output terminals and latches a digital signal applied at the input terminal responsive to a clock signal. The bus capture circuit further includes a plurality of signal delay circuits, each signal delay circuit being coupled between a respective bus line and the input terminal of a respective latch. Each signal delay circuit develops a delayed digital signal having a delay time relative to the digital signal applied on the corresponding bus line, and applies the delayed digital signal to the input terminal of the corresponding latch. A control circuit is coupled to the signal delay circuits and to the output terminals of the latches. The control circuit adjusts the delay time of each signal delay circuit as a function of the data eye of the digital signal applied on the input of the signal delay circuit. In this way, the bus capture circuit adjusts the respective delay time of each signal delay circuit such that the corresponding latch successfully latches the delayed digital signal output from the signal delay circuit responsive to an applied clock signal.
According to a second aspect of the present invention, the control circuit also operates in a monitoring mode of operation to detect shifts in the data eye of an external clock signal. When the control circuit detects such a shift, the control circuit adjusts the delay time of all signal delay circuits by a delay adjustment time. According to another aspect of the present invention, the bus capture circuit is contained in a packetized memory device, such as an SLDRAM, and operates during an initialization mode of operation to adjust the delay times of each signal delay circuit as a function of the data eye of the digital signal applied on the input of that signal delay circuit.